The present application relates to a semiconductor structure and a method of forming the same. More particularly, the present application relates to a semiconductor structure including a liner-free or partial liner-free contact/via structure that is embedded within a dielectric capping layer and positioned between an electrically conductive structure and an overlying contact structure.
Generally, BEOL interconnect devices include a plurality of circuits which form an integrated circuit fabricated on a BEOL interconnect substrate. A complex network of signal paths will normally be routed to connect the circuit elements distributed on the surface of the substrate. Efficient routing of these signals across the device requires formation of multilevel or multilayered schemes, such as, for example, single or dual damascene wiring, i.e., interconnect, structures.
Within typical BEOL interconnect structures, electrically conductive metal vias run perpendicular to the BEOL interconnect substrate and electrically conductive metal lines run parallel to the BEOL interconnect substrate. Typically, the electrically conductive metal vias are present beneath the electrically conductive metal lines and both features are embedded within an interconnect dielectric material layer.
In multilayered BEOL interconnect structures, a dielectric capping layer containing a contact/via opening is located between a lower interconnect dielectric material and an upper interconnect dielectric material. Compared to both the lower and upper interconnects, liner/barrier volume fraction increases faster inside the contact/via feature, while scaling the overall BEOL dimensions. Accordingly, it would be beneficial to decouple the metallization process between line and via features in order to optimize the overall BEOL interconnect performance.